RK3568 · DesignWare GMAC

DW GMAC / RK3568

RK3568

Rockchip · ARM Cortex-A55 四核 · 2GHz

···Armory 获取

1G×2网口速率

RGMIIPHY 接口

TSO硬件卸载

PTP硬件时间戳

板卡配置

设备树基本配置

RK3568 的 DW GMAC 控制器公共节点用于描述 GMAC0 / GMAC1 的寄存器、中断、时钟、复位、MDIO 与 DMA 队列等基础资源。不同板卡通常只需要在此基础上覆盖 clock_in_out、tx_delay、rx_delay、PHY 复位 GPIO、时钟父节点和 status 等板级参数。

查看 RK3568 DW GMAC 公共设备树配置包含 GMAC0 / GMAC1 控制器基础节点

gmac0: ethernet@fe2a0000 {
  compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
  reg = <0x0 0xfe2a0000 0x0 0x10000>;
  interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
          <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
  interrupt-names = "macirq", "eth_wake_irq";
  rockchip,grf = <&grf>;
  clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
      <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
      <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
      <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
      <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>;
  clock-names = "stmmaceth", "mac_clk_rx",
          "mac_clk_tx", "clk_mac_refout",
          "aclk_mac", "pclk_mac",
          "clk_mac_speed", "ptp_ref",
          "pclk_xpcs", "clk_xpcs_eee";
  resets = <&cru SRST_A_GMAC0>;
  reset-names = "stmmaceth";
  snps,mixed-burst;
  snps,tso;
  snps,axi-config = <&gmac0_stmmac_axi_setup>;
  snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
  snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
  status = "disabled";
  mdio0: mdio {
    compatible = "snps,dwmac-mdio";
    #address-cells = <0x1>;
    #size-cells = <0x0>;
  };
};

gmac1: ethernet@fe010000 {
  compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
  reg = <0x0 0xfe010000 0x0 0x10000>;
  interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
          <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
  interrupt-names = "macirq", "eth_wake_irq";
  rockchip,grf = <&grf>;
  clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
      <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
      <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
      <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>,
      <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>;
  clock-names = "stmmaceth", "mac_clk_rx",
          "mac_clk_tx", "clk_mac_refout",
          "aclk_mac", "pclk_mac",
          "clk_mac_speed", "ptp_ref",
          "pclk_xpcs", "clk_xpcs_eee";
  resets = <&cru SRST_A_GMAC1>;
  reset-names = "stmmaceth";
  snps,mixed-burst;
  snps,tso;
  snps,axi-config = <&gmac1_stmmac_axi_setup>;
  snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
  snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
  status = "disabled";
  mdio1: mdio {
    compatible = "snps,dwmac-mdio";
    #address-cells = <0x1>;
    #size-cells = <0x0>;
  };
};

板级差异配置

不同板卡的差异主要在时钟方向、TX/RX delay 值和 PHY 复位 GPIO；具体板级覆盖内容见各板卡页签中的“网卡设备树配置”：

Rockchip EVB1Rockchip 官方评估板

稳定

PHY 接口rgmii

时钟方向output（SoC 驱动）

GMAC0 delaytx=0x3c / rx=0x2f

GMAC1 delaytx=0x4f / rx=0x26

PHY 复位gpio2 PD3 / gpio2 PD1

特殊说明

• clock_in_out = output，时钟由 SoC 内部 PLL（CLK_MAC_2TOP）驱动，125 MHz
• PHY 复位时序：延迟 0 / 20ms / 100ms

网卡设备树配置

&gmac0 {
    phy-mode = "rgmii";
    clock_in_out = "output";
    snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
    snps,reset-delays-us = <0 20000 100000>;
    assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
    assigned-clock-rates = <0>, <125000000>;
    tx_delay = <0x3c>;
    rx_delay = <0x2f>;
    phy-handle = <&rgmii_phy0>;
    status = "okay";
};
&gmac1 {
    phy-mode = "rgmii";
    clock_in_out = "output";
    snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
    snps,reset-delays-us = <0 20000 100000>;
    assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
    assigned-clock-rates = <0>, <125000000>;
    tx_delay = <0x4f>;
    rx_delay = <0x26>;
    phy-handle = <&rgmii_phy1>;
    status = "okay";
};

SoC 级说明

网口映射

网口	控制器基地址	IRQ
eth0 (GMAC0)	0xFE2A0000	27
eth1 (GMAC1)	0xFE010000	32

时钟配置

RK3568 GMAC 支持两种时钟模式：

• output 模式（clock_in_out = "output"）：时钟由 SoC 内部 PLL（CLK_MAC_2TOP）产生并驱动至 PHY，典型值 125 MHz；
• input 模式（clock_in_out = "input"）：时钟由外部 PHY 或晶振提供，SoC 从 gmac_clkin 接收。部分板卡还通过 CLK_MAC_OUT（25 MHz）向 PHY 提供参考时钟。

RGMII 延迟校准

RK3568 通过 GRF 寄存器控制 TX/RX 内部延迟，不同板卡因 PCB 走线不同而使用不同的 delay 值。错误的 delay 配置会导致链路不稳定或无法建立，调试时可逐步调整。

已知问题

已知PHY 自协商在 100M 半双工模式下偶发超时，建议业务侧固定速率为 1000M 全双工

← 返回 DW GMAC 更新日志